A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications(<Special Section>Analog Circuit Techniques and Related Topics)
スポンサーリンク
概要
- 論文の詳細を見る
This article describes a large bandwidth and low distortion line driver in a 0.35-μm CMOS process. The line driver drives a 75 Ω resistive load. Its power consumption is 140mW from a 3.3V supply. It has a relatively high -3 dB bandwidth (260MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3V peak to peak sine wave at 10MHz. This architecture reduces the distortion by locating the input differential pair inside the feedback loop and eliminating the distortion of the feedback transistors, which is dominant source of distortion at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.
- 社団法人電子情報通信学会の論文
- 2005-02-01
著者
-
Hadidi K
Electrical Engineering Department Ulmia University
-
Hadidi Khayrollah
Microelectronic Research Laboratory Urmia University
-
KHOEI Abdollah
Microelectronic research laboratory, Urmia University
-
Hadidi K
Microelectronics Research Laboratory Urmia University
-
Khoei A
Microelectronics Research Laboratory Urmia University
-
OSKOOEI SAVADI
Microelectronics Research Laboratory, Urmia University
-
Oskooei Savadi
Microelectronics Research Laboratory Urmia University
-
Hadidi Khayrollah
Microelectronic Research Laboratory Of Urmia University
-
Khoei Abdollah
Microelectronic Research Laboratory Of Urmia University
関連論文
- C-12-42 2.5V CMOS Fully Differential Low Power High Linearity Analog Line-Driver
- C-12-43 A Constant Bandwidth CMOS VGA ckt.
- A "Variable Capacitance" Circuit for Tuning Integrated Filters and Oscillators
- C-12-23 A 430MHz, -47.5dB THD, Single Transconductor, 5th-OrderLow-Pass Filter in a 0.5μm CMOS Process
- C-12-33 CMOS スイッチトキャパシタ DC-DC コンバータ
- A 500MS/sec -54db THD Open-Loop CMOS Sample-and-Hold Stage
- C-12-25 A Highly Linear Open-Loop Full CMOS High-Speed Sample-and-Hold Stage
- A Novel Open Loop Structure for Phase Shifting and Frequency Synthesizing
- A Current-Mode, First-Order Takagi-Sugeno-Kang Fuzzy Logic Controller, Supporting Rational-Powered Membership Functions(Analog Circuits and Related SoC Integration Technologies)
- Design of a New Folded Cascode Op-Amp Using Positive Feedback and Bulk Amplification(Analog Circuits and Related SoC Integration Technologies)
- Design of Analog Current-Mode Loser-Take-All Circuit(Analog Circuit and Device Technologies)
- Modified CMOS Op-Amp with Improved Gain and Bandwidth(Analog Circuit and Device Technologies)
- A Low-Power, Small-Size 10-Bit Successive-Approximation ADC(Analog Signal Processing)
- A Practical, Systematic, Simple Method to Evaluate Speed/Bandwidth Potential of CMOS Processes for Analog Design and Related Practical Considerations
- A Highly Linear and Large Bandwidth Fully Differential CMOS Line Driver Suitable for High-Speed Data Transmission Applications(Analog Circuit Techniques and Related Topics)
- Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption
- High Efficiency On-Chip CMOS DC-DC Converters for Mixed Analog-Digital Low-Power ICs(Analog Circuit Techniques and Related Topics)
- A New Method for Offset Cancellation in High-Resolution High-Speed Comparators(Building Block, Analog Circuit and Device Technologies)
- A 500MS/s 600μW 300μm^2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35μm 3.3v CMOS Process
- A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations
- Ultra High Speed Modified Booth Encoding Architecture for High Speed Parallel Accumulations
- CMOS Implementation of A New High Speed 5-2 Compressor for Parallel Accumulations