A 500MS/s 600μW 300μm^2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35μm 3.3v CMOS Process
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概要
- 論文の詳細を見る
This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600µw power consumption from a 3.3v power supply by using TSMC model of 0.35µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300µm2.
- 2011-04-01
著者
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KHOEI Abdollah
Microelectronic research laboratory, Urmia University
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KAZEMINIA Sarang
Microelectronics Research Laboratory of Urmia University
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MOUSAZADEH Morteza
Microelectronics Research Laboratory of Urmia University
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HADIDI Kayrollah
Microelectronics Research Laboratory of Urmia University
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Khoei Abdollah
Microelectronic Research Laboratory Of Urmia University
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