CMOS Implementation of A New High Speed 5-2 Compressor for Parallel Accumulations
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概要
- 論文の詳細を見る
This paper presents a new high speed 5-2 compressor. It is designed based on a new truth table which leads to a simple structure. Also, the driving problems are reduced. Due to the similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays and the power dissipation is decreased. Furthermore, by use of full swing logics, the speed of cascaded operations is enhanced. The latency of proposed design is 440ps.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
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Hadidi Khayrollah
Microelectronic Research Laboratory Of Urmia University
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Khoei Abdollah
Microelectronic Research Laboratory Of Urmia University
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Hadidi Khayrollah
Microelectronic Research Laboratory, University of Urmia
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Abolhasani Alireza
Microelectronic Research Laboratory, University of Urmia
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Tohidi Mohammad
Microelectronic Research Laboratory, University of Urmia
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Khoei Abdollah
Microelectronic Research Laboratory, University of Urmia
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