Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
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概要
- 論文の詳細を見る
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-06-30
著者
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LEE Sung-Woo
Process Development Team. Samsung Electronic Co., Ltd.
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HAN Woo-Sung
Process Development Team. Samsung Electronic Co., Ltd.
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Cho Han-ku
Process Development Team Semiconductor R&d Center Samsung Electronics
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Lee Jung-hyeon
Process Development Team Semiconductor R&d Center Samsung Electronics
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LEE Doo-Youl
Process Development Team, Semiconductor R&D Center, Samsung Electronics
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YEO Gi-Sung
Process Development Team, Semiconductor R&D Center, Samsung Electronics
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- Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
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- Hot-Spot Detection and Correction Using Full-Chip-Based Process Window Analysis
- Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
- A New Method for Line Width Roughness Mitigation
- Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography