Cho Han-ku | Process Development Team Semiconductor R&d Center Samsung Electronics

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著作論文

Most Efficient Alternative Manner of Patterning sub-80nm Contact Holes and Trenches with 193nm Lithography
Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
Double-Patterning Technique Using Plasma Treatment of Photoresist
Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
A New Method for Line Width Roughness Mitigation
Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography

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