Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
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概要
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In order to control the on-chip linewidth variation (OCV) in logic devices, accurate optical proximity correction (OPC) is required, and the method to enhance its result is devised. The optical proximity behaviors are severely varied according to the optical and material conditions. The change in photoresist (PR) species deteriorates the OPC rule from 9.3 nm to 15.1 nm for two kinds of PR species. The illumination condition variation also deteriorates the optical-proximity-corrected (OPCed) results from 9.3 nm to 11.6 nm. To obtain accurate OPCed results, these conditions should be fixed. For improving the correction accuracy of the optical proximity, the OPCed grid size effect on the critical dimension (CD) uniformity is evaluated quantitatively. By adopting the OPC grid size of less than 1 nm, the correction resolution limited by the grid size is enhanced. The selective bias with the assist features is applied to the line-and-space (L/S) patterns varied by the space sizes. The selective bias rule is generated with a model using the different grid sizes of 1 nm and 0.5 nm. In the nominal CD of 87 nm, the $3\sigma$ values of the optical proximity effect are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The improvement of 9.2 nm is achieved, corresponding to nearly 39% enhancement. The CD uniformity dependence on the grid size was characterized in two-dimensional pattern on a real static random access memory (SRAM) pattern with the different grid sizes of 1 nm and 0.5 nm. The $3\sigma$ values of the uniformity are 9.9 nm and 8.7 nm in the case of grid sizes of 1 nm and 0.5 nm, respectively. Decreasing the grid size improves the uniformity by 4.7 nm, corresponding to 22% enhancement. By considering the mask error enhancement factor (MEEF), the enhanced amount is calculated to be 3.2 nm. The pattern fidelity improvement in the mask by reducing the grid size enhances the printing images, and decreases the measurement error using the in-line CD scanning electron microscope (SEM).
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2004-06-15
著者
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Cho Han-ku
Process Development Team Semiconductor R&d Center Samsung Electronics
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Lee Jung-hyeon
Process Development Team Semiconductor R&d Center Samsung Electronics
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Han Woo-sung
Process Development Team Semiconductor R&d Center Samsung Electronics
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Lee Sung-woo
Process Development Team Semiconductor R&d Center Samsung Electronics
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Lee Sung-Woo
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 499-711, Korea
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Lee Doo-Youl
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #16, Banwol-Dong, Hwasung, Gyeonggi-Do 445-701, Korea
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Han Woo-Sung
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 499-711, Korea
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Yeo Ci-Sung
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 499-711, Korea
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Cho Han-Ku
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 499-711, Korea
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Lee Jung-Hyeon
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 499-711, Korea
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Yeo Gi-Sung
Process Development Team, Semiconductor R&D Center, Samsung Electronics, San #24, Nongseo-Ri, Giheung-Eup, Yongin-City, Gyeonggi-Do 499-711, Korea
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