A New Method for Line Width Roughness Mitigation
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概要
- 論文の詳細を見る
Demands of the continuous downscaling of device size impose stringent requirements on the RLS trade-off (R: resolution, L: line width roughness and S: sensitivity). Among the above, line width roughness (LWR) has to be controlled below 10% of critical dimensions (CD). While significant improvement in R&S was achieved, LWR has been relatively high for extreme ultra-violet lithography resists. Herein, we provide a new method for LWR mitigation that overcomes several shortcomings of previously known methods. Our new method is based on a double development method wherein, a polymeric solution in developer is coated on to the patterned surface. The wafer is then subjected to the standard development step during which LWR improvement is affected. In this paper we discuss the hypothesis of our method and provide relevant data to understand the conditions under which LWR improvement is observed. Effect of polymer/developer concentration ratio, solid content and bake temperatures will be discussed. Also, our method will be compared with currently available methods for LWR improvement on pattern transfer.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2011-06-25
著者
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Cho Han-ku
Process Development Team Semiconductor R&d Center Samsung Electronics
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Yool Kang
Process Development Team, Semiconductor R&D Center, Samsung Electronics, Hwasung, Gyeonggi 445-701, Korea
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Kim Hochul
Process Development Team, Semiconductor R&D Center, Samsung Electronics, Hwasung, Gyeonggi 445-701, Korea
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Cho Han-Ku
Process Development Team, Semiconductor R&D Center, Samsung Electronics, Hwasung, Gyeonggi 445-701, Korea
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Mayya K.
Process Development Team, Semiconductor R&D Center, Samsung Electronics, Hwasung, Gyeonggi 445-701, Korea
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Mayya K.
Process Development Team, Semiconductor R&D Center, Samsung Electronics, Hwasung, Gyeonggi 445-701, Korea
関連論文
- Most Efficient Alternative Manner of Patterning sub-80nm Contact Holes and Trenches with 193nm Lithography
- Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
- Double-Patterning Technique Using Plasma Treatment of Photoresist
- Quantitative Evaluation of Grid Size Effect on Critical Dimension Uniformity Improvement
- A New Method for Line Width Roughness Mitigation
- Most Efficient Alternative Manner of Patterning sub-80 nm Contact Holes and Trenches with 193 nm Lithography