低雑音センサインターフェース回路に向けた JFET 混載 CMOS 技術

概要

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In this paper, fabrication technology and device characteristics of junction field effect transistor (JFET) which can be integrated in CMOS sensor interface circuits are presented. The JFET is applicable to CMOS (operational) amplifiers to realize a very low-noise front-end amplifier in sensor interface circuits. It is formed with isolated p-well area in CMOS device. Extra processes to a standard CMOS technology are one photolithography process and two ion-implantation processes. N-type channel in JFET is formed by deep ion-implantation of phosphorous with energy of 150 keV to connect n+ source and drain regions. After that, p-type top gate region is formed by shallow ion-implantation of borron with energy of 30 keV. Fabricated JFET devices showed enough transconductance and low drain conductance, which are suitable to use them in analog amplifiers. Noise power-spectrum of the fabricated JFET was evaluated, and compared with n-MOSFET and p-MOSFET. As a result, noise-spectrum of JFET below 1 kHz was much lower than that of CMOS devices. Since many physical sensors have their signal bandwidth in low frequency band, this JFET device can be utilized in CMOS-based front-end amplifiers as the key device of low-noise sensor interface circuits.
社団法人電気学会の論文
2003-10-01