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VLSI Design and Education Center, the University of Tokyo | 論文
- A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS
- Performance-Constrained Transistor Sizing for Different Cell Count Minimization
- AI-1-4 超ディペンダブルVLSIへの挑戦(AI-1.デイベンダブルVLSIに向けて,依頼シンポジウム,ソサイエティ企画)
- Synchronization Verification in System-Level Design with ILP Solvers(System Level Design,VLSI Design and CAD Algorithms)
- EFSM-based Weight-oriented Concolic Testing for Embedded Software
- Instruction-Level Power Estimation Method by Considering Hamming Distance of Registers(Selected Papers from the 16th Workshop on Circuits and Systems in Karuizawa)
- Fully-Parallel VLSI Implementation of Vector Quantization Processor Using Neuron-MOS Technology (Special Issue on Integrated Electronics and New System Paradigms)
- A 100Mbps, 4.1pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90nm CMOS
- An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors(Analog and Communications,Low-Power, High-Speed LSIs and Related Technologies)
- Reducing scheduling overheads in dynamically reconfigurable processors (VLSI設計技術)
- Reducing scheduling overheads in dynamically reconfigurable processors (コンピュータシステム)
- Reducing scheduling overheads in dynamically reconfigurable processors (リコンフィギャラブルシステム)
- An Efficient Motion Estimation Algorithm Using a Gyro Sensor(Video/Image Coding)(Applications and Implementations of Digital Signal Processing)
- A 1.76mW, 100Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS
- The AMS Extension to System Level Design Language-SpecC(System Level Design,VLSI Design and CAD Algorithms)
- Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment(Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
- Single-Electron Circuit Simulation (Special Issue on Technology Challenges for Single Electron Devices)
- Proposal of a Schottky-Barrier SET Aiming at a Future Integrated Device (Special Issue on New Concept Device and Novel Architecture LSIs)
- Correlated Electron-Hole Transport in Capacitively-Coupled One-Dimensional Tunnel Junction Arrays ( Quantum Dot Structures)
- Circuit Simulators Aiming at Single-Electron Integration