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VLSI Design and Education Center, the University of Tokyo | 論文
- Word-Level Equivalence Checking in Bit-Level Accuracy by Synthesizing Designs onto Identical Datapath
- Interconnect-Aware Pipeline Synthesis for Array-Based Architectures
- Single-Electron Transistor in Silicon-on-Insulator with Schottky-Contact Tunnel Barriers ( Quantum Dot Structures)
- Multi-Level Bounded Model Checking with Symbolic Counterexamples
- A Unified Framework for Equivalence Verification of Datapath Oriented Applications
- An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences(Simulation and Verification, VLSI Design and CAD Algorithms)
- An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging
- EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution
- Transaction Ordering in Network-on-Chips for Post-Silicon Validation
- Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering
- Data Flow Graph Partitioning Algorithms and Their Evaluations for Optimal Spatio-temporal Computation on a Coarse Grain Reconfigurable Architecture
- Performance Estimation with Automatic False-Path Detection for System-Level Designs
- Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability
- Custom Instruction Generation for Configurable Processors with Limited Numbers of Operands
- Trends in Formal Verification Techniques for C-based Hardware Designs
- Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering
- Exact Minimum Factoring of Incompletely Specified Logic Functions via Quantified Boolean Satisfiability