Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

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概要

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• In order to cope with the increasing leakage power and the increasing device variability in VLSI's, the required control size of both the space-domain and the time-domain is decreasing. This paper shows the several recent fine-grain voltage engineerings for the low power VLSI circuit design. The space-domain fine-grain voltage engineering includes the fine-grain power supply voltage with 3D-structured on-chip buck converters with the maximum power efficiency up to 71.3% in 0.35_?m CMOS and the fine-grain body bias control to reduce power supply voltage in 90-nm CMOS. The time-domain fine-grain voltage engineering includes accelerators for the power supply voltage hopping with a 5-ns transition time in 0.18-?m CMOS, the power supply noise canceller with the 32% power supply noise reduction in 90-nm CMOS, and backgate bias accelerators for fast wake-up with 1.5-V change of backgate voltage in 35 ns in 90-nm CMOS.

• 一般社団法人情報処理学会の論文
• 2009-02-17

著者

• Makoto Takamiya

  VLSI Design and Education Center, the University of Tokyo

• Takayasu Sakurai

  Institute of Industrial Science, the University of Tokyo

関連論文

• Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering

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