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NTT Basic Research laboratories, NTT Corporation | 論文
- 20aHW-9 Fast tuning the gap of a superconducting flux qubit
- Al2O3 Insulated-Gate Structure for AlGaN/GaN Heterostructure Field Effect Transistors Having Thin AlGaN Barrier Layers
- Effect of UV/ozone Treatment of Nanogap Electrodes for Molecular Devices
- Nucleus and Spiral Growth Mechanisms of GaN Studied by Using Selective-Area Metalorganic Vapor Phase Epitaxy
- A Field-Effect Transistor with a Deposited Graphite Thin Film
- Novel-Functional Single-Electron Devices Using Silicon Nanodot Array
- Fabrication of double-dot single-electron transistor in silicon nanowire
- Novel-Functional Single-Electron Devices Using Silicon Nanodot Array
- Fabrication of double-dot single-electron transistor in silicon nanowire
- Single-Electron-Resolution Electrometer Based on Field-Effect Transistor(Session4B: Emerging Devices II)
- Single-Electron-Resolution Electrometer Based on Field-Effect Transistor(Session4B: Emerging Devices II)
- Capacitive Parameter Extraction for Nanometer-Size Field-Effect Transistors
- Transfer and Detection of Single Electrons Using Metal-Oxide-Semiconductor Field-Effect Transistors(Emerging Devices,Fundamentals and Applications of Advanced Semiconductor Devices)
- Charge-State Control of Phosphorus Donors in Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor
- Multifunctional Boolean Logic Using Single-Electron Transistors(New System Paradigms for Integrated Electronics)
- Analysis of Back-Gate Voltage Dependence of Threshold Voltage of Thin Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect Transistor and Its Application to Si Single-Electron Transistor
- A Multiple-Valued Logic and Memory With Combined Single-Electron and Metal-Oxide-Semiconductor Transistors
- A Merged Single-Electron Transistor and Metal-Oxide-Semiconductor Transistor Logic for Interface and Multiple-Valued Functions
- Multipeak negative-differential-resistance device by combining single-electron and metal-oxide-semiconductor transistors
- A Merged SET-MOSFET Logic for Interface and Multiple-Valued Functions