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Hitachi ULSI Systems Co., Ltd. | 論文
- A 126mm^2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology(Integrated Electronics)
- A Hierarchical Timing Adjuster Featuring Intermittent Measurement for Use in Low-Power DDR SDRAMs
- μI/O Architecture : A Power-Aware Interconnect Circuit Design for SoC and SiP(Low-Power System LSI, IP and Related Technologies)
- HCI-Free Selective Epitaxial SiGe Growth by LPCVD for 80-GHz BiCMOS Production
- The Umbrella Cell : A High-Density 2T Cell for SOC Applications(Memory, Low-Power LSI and Low-Power IP)
- Reducing Consuming Clock Power Optimization of a 90 nm Embedded Processor Core (Low Power Techniques, VLSI Design Technology in the Sub-100nm Era)
- A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications(Special Issue on High-Performance and Low-Power Microprocessors)
- A 130-nm CMOS 95-mm^2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput(Integrated Electronics)
- Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
- Measurement of Inner-chip Variation and Signal Integrity By a 90-nm Large-scale TEG
- A 12.5-ns 16-Mb CMOS SRAM with Common-Centroid-Geometry-Layout Sense Amplifiers (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
- A Physical Synthesis Methodology for Multi-Threshold-Voltage Design in Low-Power Embedded Processor(Low-Power System LSI, IP and Related Technologies)