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Graduate School of Information Sciences Tohoku University | 論文
- Relative Clauses in a Minimalist Framework
- Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification(Novel Device Architectures and System Integration Technologies)
- Low-Power Field-Programmable VLSI Using Multiple Supply Voltages(Low Power Methodology, VLSI Design and CAD Algorithms)
- C-12-4 Low Power Field Programmable VLSI Processor Using Multiple Supply Voltages
- Field-Programmable VLSI Based on a Bit-Serial Fine-Grain Architecture(New System Paradigms for Integrated Electronics)
- Highly-Parallel Stereo Vision VLSI Processor Based on an Optimal Parallel Memory Access Scheme
- An FPGA-Oriented Motion-Stereo Processor with a Simple Interconnection Network for Parallel Memory Access
- Architecture of a high-performance stereo vision VLSI processor
- Collision Detection VLSI Processor for Highly-Safe Intelligent Vehicles Using a Multiport Content-Addressable Memory
- A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
- Generalized Hough Transform VLSI Processor for Model-Based Edge Detection
- Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture
- Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages
- Memory Allocation for Multi-Resolution Image Processing
- Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
- Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment
- Design of a Reconfigurable Parallel Processor for Digital Control Using FPGAs (Special Issue on Super Chip for Intelligent Integrated Systems)
- High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems (Special Issue on Super Chip for Intelligent Integrated Systems)
- Pixel-Serial and Window-Parallel VLSI Processor for Stereo Matching Using a Variable Window Size
- Multiple-Valued Programmable Logic Array Based on a Resonant-Tunneling Diode Model