High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems (Special Issue on Super Chip for Intelligent Integrated Systems)

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概要

• 論文の詳細を見る

• In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors for intelligent integrated systems with small latency becomes a very important subject. In this paper, we present a scheduling algorithm for high-level synthesis. The input to the scheduler is a behavioral description which is viewed as a data flow graph (DFG). The scheduler minimizes the latency, which is the delay of the critical path in the DFG, and minimizes the number of functional units and buses by improving the utilization rates. By using an integer linear programming, the scheduler optimally assigns nodes and arcs in the DFG into steps.

• 社団法人電子情報通信学会の論文
• 1994-07-25

著者

• Kameyama Michitaka

  Faculty of Engineering, Tohoku University

• Kameyama Michitaka

  Faculty Of Engineering Tohoku University

• Sawano Yasuaki

  Graduate School of Information Sciences, Tohoku University

• Kim Bumchul

  Graduate School of Information Sciences, Tohoku University

• Kim Bumchul

  Graduate School Of Information Sciences Tohoku University

• Sawano Yasuaki

  Graduate School Of Information Sciences Tohoku University

関連論文

• Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation (Special Issue on Multiple-Valued Integrated Circuits)
• Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation (Special Issue on Multiple-Valued Integrated Circuits)
• High-Level Synthesis of VLSI Processors for Intelligent Integrated Systems (Special Issue on Super Chip for Intelligent Integrated Systems)
• Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements (Special Issue on Multiple-Valued Integrated Circuits)

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