Multiple-Valued VLSI Image Processor Based on Residue Arithmetic and Its Evaluation (Special Issue on Multiple-Valued Integrated Circuits)

概要

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The demand for high-speed image processing is obvious in many real-world computations such as robot vision. Not only high throughput but also small latency becomes an important factor of the performance, because of the requirement of frequent visual feedback. In this paper, a high-performance VLSI image processor based on the multiple-valued residue arithmetic circuit is proposed for such applications. Parallelism is hierarchically used to realize the high-performance VLSI image processor. First, spatially parallel architecture that is different from pipeline architecture is considered to reduce the latency. Secondly, residue number arithmetic is introduced. In the residue number arithmetic, data communication between the mod m_i arithmetic units is not necessary, so that multiple mod m_i arithmetic units can be completely separated to different chips. Therefore, a number of mod m_i multiply adders can be implemented on a single VLSI chip based on the modulus-slice concept. Finally, each mod m_i arithmetic unit can be effectively implemented in parallel structure using the concept of a pseudo-primitive root and the multiple-valued current-mode circuit technology. Thus, it is made clear that the throughout use of parallelism makes the latency 1 / 3 in comparison with the ordinary binary implementation.
社団法人電子情報通信学会の論文
1993-03-25