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Faculty of Engineering, and VLSI Design and Education Center (VDEC), the University of Tokyo | 論文
- Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability
- A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells(Computer Components)
- A High-Speed and Area-Efficient Dual-Rail PLA Using Divided and Interdigitated Column Circuits(Integrated Electronics)
- A Logic-Cell-Embedded PLA (LCPLA) : An Area-Efficient Dual-Rail Array Logic Architecture(Integrated Electronics)
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- Performance Driven Design Methodology for a Dual-Rail PLA with 2-Input Logic Cells
- A-3-7 A Module Generator for a Dual-Rail PLA with 2-Input Logic Cells
- A High-Speed PLA Using Dynamic Array Logic Circuits with Latch Sense Amplifiers
- A Structural Approach for Transistor Circuit Synthesis(Circuit Synthesis,VLSI Design and CAD Algorithms)
- Pixel-Level Color Demodulation Image Sensor for Support of Image Recognition(Electronic Circuits)
- Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories(New System Paradigms for Integrated Electronics)
- A Row-Parallel Position Detector for High-Speed 3-D Camera Based on Light-Section Method(Electronic Circuits)
- High-Sensitivity and Wide-Dynamic-Range Position Sensor Using Logarithmic-Response and Correlation Circuit
- A Quantum Algorithm for Searching Web Communities
- Cascaded Time Difference Amplifier with Differential Logic Delay Cell
- 1.0ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells