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Department Of Electronic And Electrical Engineering Pohang University Of Science And Technology | 論文
- A two-layer stacked polycrystalline silicon thin film transistor complementary metal oxide semiconductor inverters using laser crystallized channel with high-k and metal gate on Si (Special issue: Solid state devices and materials)
- Fabrication of Two-Layer stacked Poly-Si TFT CMOS Inverters Using Laser Crystallized channel with metal gate on Si Substrate
- SOI-Based Nanoscale CMOS Device Technology(Session 6A Silicon Devices III,AWAD2006)
- Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications(Session 4 Silicon Devices II,AWAD2006)
- SOI-Based Nanoscale CMOS Device Technology(Session 6A Silicon Devices III,AWAD2006)
- Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications(Session 4 Silicon Devices II,AWAD2006)
- SOI-Based Nanoscale CMOS Device Technology
- Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications
- Analysis of Interface Property of SiGe-On-Insulator (SGOI) Substrate with a Strained-Si Layer for Nano-CMOS Device Applications
- Ultrashallow Junction Formation Using Novel Plasma Doping Technology beyond 50nm MOS Devices
- Ultra-Shallow Junction Formation using Novel Plasma Doping Technology beyond 50nm MOS Devices
- Fabrication of 50nm Trigate Silicon On Insulator Metal-Oxide-Silicon Field-Effect Transistor without Source/Drain Activation Annealing
- Low-Temperature-Processed Polycrystalline Silicon Thin-Film Transistors Using Titanium Disilicide Contacts for Source and Drain
- Three-Level Charge-Pumping Technique for Grain-Boundary Trap Evaluation in Polysilicon Thin Film Transistors
- Prevention of Oxygen Incorporation in poly-Si_Ge_x Deposition with Interfacial Amorphous Silicon Layer
- Characterization of Proximity Correction in 100-nm-Regime X-Ray Lithography
- Novel Sub-10nm Polymer Thin Film Resistance Switching Device
- Identification of Grain-Boundary Trap Properties Using Three-Level Charge-Pumping Technique in Polysilicon Thin-Film Transistors
- Spatially-Controllable Quantum Well Intermixing with Stripe-Size Dependence in AlGaAs Heterostructures
- A Technique for Extracting Small-Signal Equivalent-Circuit Elements of HEMTs (Special Issue on High-Frequency/speed Devices in the 21st Century)