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Central Research Laboratory, HITACHI, Ltd. | 論文
- Nondestructive Measurement of Minority Carrier Lifetimes in Si Wafers Using Frequency Dependence of ac Photovoltages
- Measurement of Minority Carrier Lifetimes using AC Photovoltages Excited by Two Photon Beams of Different Wavelengths
- A Non-Destructive Method for Measuring Lifetimes for Minority Carriers in Semiconductor Wafers Using Frequency-Dependent ac Photovoltages
- Characteristics of Silicon Solar Cells Fabricated by Non-Mass-Analyzed Ion Implantation : I-1: SILICON SOLAR CELLS (1) : Ion Implantation & Radiation damage
- A Photovoltaic Method for Evaluating Junction Characteristics Using Cut-Off Frequency
- High-Power Microwave-Induced Plasma Source for Trace Element Analysis
- Heuristic Method for Phase-Conflict Minimization in Automatic Phase-Shift Mask Design
- Analysis of Nonplanar Topography Effects of Phase Shift Masks on Imaging Characteristics
- 0.13 μm Pattern Delineation Using KrF Excimer Laser Light
- Algorithm for Phase-Shift Mask Design with Priority on Shifter Placement
- Phase-Shifting Technology for ULSI Patterning (Special Issue on Opto-Electronics and LSI)
- Novel Alignment Method for Planarized Substrates in Electron Beam Lithography
- Investigation of the Electron Nonradiative Transition in Extremely Thin GaInNAs/GaAs Single Quantum Well by Using a Piezoelectric Photothermal Spectroscopy
- Slurry Chemical Corrosion and Galvanic Corrosion during Copper Chemical Mechanical Polishing
- Direct Wafer Bonding Technique Aiming for Free-Material and Free-Orientation Integration of Semiconductor Materials
- Portable Digital Satellite News Gathering (SNG) RF Terminal Using a Flat Antenna : PAPER Special Issue on Digital Broadcasting Technology (Special Issue on Digital Broadcasting Technology)
- Ac Surface Photovoltages in p-Type Silicon Wafers Oxidized in Water-Free and Wet Ambients
- Ac Surface Photovoltages in Strongly-Inverted Oxidized p-Type Silicon Wafers^*
- Characterization of Line-edge Roughness in Cu/low-k Interconnect Pattern
- A Novel Laser Annealing Process for Advanced CMOS with Suppressed Gate Depletion and Ultra-shallow Junctions