OOWAKI Yukihito | Research amp Development Center, ULSI Research Laboratories, Toshiba Corporation

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著作論文

New α-Particle Induced Soft Error Mechanism in a Three Dimensional Capacitor Cell
Folded Bitline Architecture for a Gigabit-Scale NAND DRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)
Open/Folded Bit-Line Arrangement for Ultra-High-Density DRAM's (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
Standby/Active Mode Logic for Sub-1-V Operating ULSI Memory (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))
An Ultra Low Voltage SOI CMOS Pass-Gate Logic (Special Issue on SOI Devices and Their Process Technologies)
A 250 mV Bit-Line Swing Scheme for 1-V Operating Gigabit Scale DRAMs (Special Issue on Low-Power LSI Technologies)

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