An Ultra Low Voltage SOI CMOS Pass-Gate Logic (Special Issue on SOI Devices and Their Process Technologies)
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概要
- 論文の詳細を見る
An ultra low voltage CMOS pass-gate logic using body-bias controlled SOI MOSFETs has been developed. The logic is composed of gate-body connected SOI pass-gates and a CMOS buffer with the body-bias controlled by the complementary double-rail input. The full-adder using the proposed logic improved the lowest operation voltage by 27%, compared with the SOI CPL (Complementary Pass-Gate Logic). For a 16×16 bit multiplier, the power-delay product achieved 70 pJ (including 50 pF I/O) at 0.5V power supply, which was more than 1 order of magnitude improvement over the bulk CPL.
- 社団法人電子情報通信学会の論文
- 1997-03-25
著者
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WATANABE Shunji
Nikon Corporation
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Watanabe Souichi
The Niigata Institute Of Technology
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Fuse T
Research Amp Development Center Ulsi Research Laboratories Toshiba Corporation
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Matsunaga Jun'ichi
Microelectronics Engineering Laboratory Toshiba Corporation
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Yoshimi Makoto
Advanced Semiconductor Devices Research Laboratories Toshiba Corporation
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Yoshimi M
R&d Center Kawasaki‐shi Jpn
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Terauchi M
Advanced Semiconductor Devices Research Laboratories Toshiba Corporation
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Watanabe S
Fujitsu Lab. Ltd. Kawasaki‐shi Jpn
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FUSE Tsuneaki
Research amp Development Center, ULSI Research Laboratories, Toshiba Corporation
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OOWAKI Yukihito
Research amp Development Center, ULSI Research Laboratories, Toshiba Corporation
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TERAUCHI Mamoru
Research amp Development Center, ULSI Research Laboratories, Toshiba Corporation
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WATANABE Shigeyoshi
Research amp Development Center, ULSI Research Laboratories, Toshiba Corporation
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YOSHIMI Makoto
Research amp Development Center, ULSI Research Laboratories, Toshiba Corporation
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OHUCHI Kazunori
Research amp Development Center, ULSI Research Laboratories, Toshiba Corporation
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Oowaki Yukihito
Research Amp Development Center Ulsi Research Laboratories Toshiba Corporation
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Ohuchi Kazunori
Research Amp Development Center Ulsi Research Laboratories Toshiba Corporation
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