Omura Yasuhisa | Ordist Dept. Electronics Kansai University

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概要

• 同名の論文著者
• Ordist Dept. Electronics Kansai Universityの論文著者

関連著者

• Omura Yasuhisa

  Ordist Dept. Electronics Kansai University

• Omura Yasuhisa

  ORDIST and Graduate School of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

• Omura Yasuhisa

  ORDIST and Graduate School of Engineering Science, Kansai University, Suita, Osaka 564-8680, Japan

• Sato Shingo

  Graduate School Of Engineering Hokkaido University

• Omura Yasuhisa

  Ordist:graduate School Japan Of Engineering2 Kansai University

• Omura Yasuhisa

  Ordist Grad. School Of Sci. & Eng. Kansai University

• Iida Yukio

  Ordist Dept. Electronics Kansai University

• TAMURA Takuta

  ORDIST Dept. Electronics, Kansai University

• NAMURA Shigeo

  ORDIST Dept. Electronics, Kansai University

• Yamamura Tsuyoshi

  Graduate School Of Sci. & Eng Kansai University

• Yoshimoto Kazuhisa

  Graduate School Japan Of Engineering2 Kansai University

• Tamura Takuta

  Ordist Dept. Electronics Kansai University

• Namura Shigeo

  Ordist Dept. Electronics Kansai University:(present Office)glory Corp

• Yoshioka Yoshimasa

  Ordist Grad. School Of Sci. & Eng. Kansai University

• AZUMA Yu

  ORDIST, Grad. School of Sci. & Eng., Kansai University

• Azuma Yu

  Ordist Grad. School Of Sci. & Eng. Kansai University

• Sato Shingo

  ORDIST and Graduate School of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

• Sato Shingo

  Graduate School of Science and Technology, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

• Yamamura Tsuyoshi

  ORDIST and Graduate School of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

• Omura Yasuhisa

  ORDIST, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

• Yamamura Tsuyoshi

  Graduate School of Science and Technology, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

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著作論文

• Performance Evaluation of Fully-Depleted SOI MOSFET-Based Diodes Applied to Schenkel Circuit for RF-ID Chips
• Design Feasibility and Prospect of High-Performance Sub-50-nm-Channel Silicon-on-Insulator Single-Gate SOI MOSFET(ELECTRICAL AND ELECTRONIC ENGINEERING,50th anniversary edition)
• Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels
• Cross-Current SOI MOSFET Model and Important Aspects of CMOS Operations
• Phonon-Limited Electron Mobility Behavior and Inherent Mobility Reduction Mechanism of Ultrathin Silicon-on-Insulator Layer with (111) Surface and Ultrathin Germanium-on-Insulator Layer with (001) Surface

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