Modeling Geometry-Dependent Floating-Body Effect Using Body-Source Built-In Potential Lowering for SOI Circuit Simulation
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概要
- 論文の詳細を見る
This paper presents a compact silicon-on-insulator (SOI) model to capture the geometry-dependent floating-body effect using the body-source built-in potential lowering approach. This physically accurate model circumvents the modeling challenge imposed by the trend of the coexistence of partial-depletion (PD) and full-depletion (FD) devices in a single SOI chip by considering short-channel, reverse short-channel and reverse narrow-width floating-body effects. The implication on circuit simulation, under the unified Berkeley short-channel IGFET model-silicon-on-insulator (BSIMSOI) framework, has also been addressed. This geometry-dependent body-source built-in potential lowering model will further enhance the device design of scaled SOI complementary metal-oxide-semiconductor (CMOS) below 100 nm.
- Published by the Japan Society of Applied Physics through the Institute of Pure and Applied Physicsの論文
- 2005-04-15
著者
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Su Pin
Department Of Electronics Engineering National Chiao Tung University
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Lee Wei
Department Of Electrical Engineering Tamkang University
-
Su Pin
Department of Electronics Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu Taiwan
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Lee Wei
Department of Electronics Engineering, National Chiao Tung University, 1001 Ta-Hsueh Road, Hsinchu Taiwan
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