Au Bump Interconnection in 20 μm Pitch on 3D Chip Stacking Technology
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概要
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The three-dimensional (3D) chip stacking LSI technology under development in Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology for realizing high-density and high-speed transmission, and superfine flip-chip bonding technologies utilizing 20-μm-pitch micro bumps on Cu through hole electrodes are substantial technologies. There are two key technical issues involved in realizing the 3D chip stacking LSI. One is the provision of the sufficient interconnections, which have low resistivity and which are absolutely connected. Another is the reduction of the thermal stress of the micro bumps by providing encapsulated resin between devices. Regarding the metallurgically stable and low electrical resistance interconnections, electroplated Au bump bonding in 20-μm-pitch by thermo compression bonding process was evaluated on the chip-on-chip(COC) structure. First, the softening of the Au bump by annealing was confirmed, and was expected to decrease the bonding stress of the under bump structure. Second, the lower limit bonding conditions were confirmed to be a bonding force of 24.5 N at 350°C, and the electrical resistance was confirmed to be stable at about 0.55 $\Omega$. The mechanism of Au–Au thermo compression bonding with the solid phase diffusion across the boundary was confirmed. Finally, the life of the 20-μm-pitch interconnection with the underfillresin containing the hyperfine filler particles under temperature cycling tests (TCT) was more than 1000 cycles, which is an acceptable level for a semiconductor package. This research will enable the realization of 3D chip stacking LSI in the near future which features scalability and high performance. The subjects are the verification of the appropriate bump dimensions in order to further improve the reliability and the realization of the interconnection reliability on 3D chip stacking LSI.
- 2003-10-15
著者
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Tomita Yoshihiro
Tsukuba Research Center Electronic System Integration Technology Research Department Association Of
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Tanaka Naotaka
Tsukuba Research Center Electronic System Integration Technology Research Department Association Of
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TAKAHASHI Kenji
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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MORIFUJI Tadahiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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Umemoto Mitsuo
Tsukuba Research Center Electronic System Integration Technology Research Department Association Of
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TANIDA Kazumasa
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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KAJIWARA Ryoichi
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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Ando Tatsuya
Tsukuba Research Center Electronic System Integration Technology Research Department Association Of
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Morifuji Tadahiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Tanaka Naotaka
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Tanida Kazumasa
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Takahashi Kenji
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
関連論文
- Current Status of Research and Development for Three-Dimensional Chip Stack Technology
- Au Bump Interconnection in 20 μm Pitch on 3D Chip Stacking Technology
- Cu Bump Interconnections in 20 μm-Pitch at Low Temperature Utilizing Electroless Tin-Plating on 3D Stacked LSI
- Micro Bump Interconnection Technologies in 20μm Pitch on 3D System in Package
- Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20μm Pitch
- Fabrication of High-Density Wiring Interposer for 10GHz 3D Packaging Using a Photosensitive Multiblock Copolymerized Polyimide
- Micro Cu Bump Interconnection on 3D Chip Stacking Technology
- Au Bump Interconnection in 20 μm Pitch on 3D Chip Stacking Technology
- Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 μm Pitch
- Fabrication of High-Density Wiring Interposer for 10 GHz 3D Packaging Using a Photosensitive Multiblock Copolymerized Polyimide
- Current Status of Research and Development for Three-Dimensional Chip Stack Technology