Current Status of Research and Development for Three-Dimensional Chip Stack Technology
スポンサーリンク
概要
- 論文の詳細を見る
The national project of "Ultra High-Density Electronic System Integration" was initiated in 1999. This is the first project to focus on a niche area between electronic devices and systems. It aims to develop technologies for overcoming the problems in terms of performance of electronic systems. Three-dimensional (3D) LSI chip stacking, optoelectronics hybrid integration, and optimum circuit design are the technology categories. For the 3D stacking technology, a chip-based stacking technology is under extensive development that includes wafer preparation for chip stacking, wafer thinning, chip stacking, and inspection and testing. In this paper, the current development status of the 3D stacking technology, called V-STACK technology, is introduced.
- Publication Office, Japanese Journal of Applied Physics, Faculty of Science, University of Tokyoの論文
- 2001-04-30
著者
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Tomita Yoshihiro
Tsukuba Research Center Electronic System Integration Technology Research Department Association Of
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TAKAHASHI Kenji
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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TERAO Hiroshi
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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YAMAJI Yasuhiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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HOSHINO Masataka
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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SATO Tomotoshi
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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MORIFUJI Tadahiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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SUNOHARA Masahiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association o
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Bonkohara Manabu
Electronic System Integration Technology Research Department Association Of Super-advanced Electroni
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Morifuji Tadahiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), C-B-5, TCI, 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Sunohara Masahiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), C-B-5, TCI, 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Takahashi Kenji
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), C-B-5, TCI, 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Yamaji Yasuhiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), C-B-5, TCI, 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Bonkohara Manabu
Electronic System Integration Technology Research Department, Headquarter Office, Association of Super-Advanced Electronic Technologies (ASET), TIME24 Bldg. 10F, 45, Aomi 2-chome, Koto-ku, Tokyo 135-8073, Japan
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Hoshino Masataka
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), C-B-5, TCI, 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Terao Hiroshi
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), C-B-5, TCI, 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
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Tomita Yoshihiro
Tsukuba Research Center, Electronic System Integration Technology Research Department, Association of Super-Advanced Electronic Technologies (ASET), C-B-5, TCI, 1-6, Sengen 2-chome, Tsukuba, Ibaraki 305-0047, Japan
関連論文
- Current Status of Research and Development for Three-Dimensional Chip Stack Technology
- Au Bump Interconnection in 20 μm Pitch on 3D Chip Stacking Technology
- Cu Bump Interconnections in 20 μm-Pitch at Low Temperature Utilizing Electroless Tin-Plating on 3D Stacked LSI
- Micro Bump Interconnection Technologies in 20μm Pitch on 3D System in Package
- Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20μm Pitch
- Micro Cu Bump Interconnection on 3D Chip Stacking Technology
- Au Bump Interconnection in 20 μm Pitch on 3D Chip Stacking Technology
- Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 μm Pitch
- Current State of Research and Development for Electronic System Integration
- Current Status of Research and Development for Three-Dimensional Chip Stack Technology