Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs
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概要
- 論文の詳細を見る
Modern field programmable gate arrays (FPGAs) with heterogeneous resources are partially reconfigurable. Existing methods of reconfiguration-aware floorplanning have limitations with regard to homogeneous resources; they solve only a part of the reconfigurable problem. In this paper, first, a precise model for partially reconfigurable FPGAs is formulated, and then, a two-phase floorplanning approach is presented. In the proposed approach, resource distribution is taken into consideration at all times. In the first step, a resource-aware insertion-after-remove perturbation is devised on the basis of the multi-layer sequence pair constraint graphs, and resource-aware slack-based moves (RASBM) are made to satisfy resource requirements. In the second step, a resource-aware fixed-outline floorplanner is used, and RASBM are applied to pack the reconfigurable regions on the FPGAs. Experimental results show that the proposed approach is resource- and reconfiguration-aware, and facilitates stable floorplanning. In addition, it reduces the wire-length by 4-28% in the first step, and by 12% on average in the second step compared to the wire-length in previous approaches.
- The Institute of Electronics, Information and Communication Engineersの論文
著者
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Chen Song
Graduate School Of Information Production And Systems Waseda University
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Chen Song
Graduate School of IPS, Waseda University
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Yoshimura Takeshi
Graduate School of Engineering, Osaka Prefecture University, Department of Applied Materials Science, 1-1 Gakuen-cho, Sakai, Osaka 599-8531, Japan
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YOSHIMURA Takeshi
Graduate School of IPS, Waseda University
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LIU Nan
Graduate School of IPS, Waseda University
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