3,300万画素120fps CMOSイメージセンサ用カラム並列2段サイクリック型A/D変換回路の低消費電力設計

概要

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A 12-bit, two-stage cyclic analog-to-digital converter (ADC) for a 33-megapixel 120-fps CMOS image sensor with low power consumption was developed by analyzing the relationship between the processed bit number and power consumption in the first- and second-stage ADCs, respectively. The power consumption of a two-stage cyclic ADC per column driven at 120 fps was reduced to 101 µW after 12 bits were separated into the upper 4 bits of the conversion in the first-stage ADC and the lower 8 bits of the conversion in the second-stage one. It exhibits a maximum differential non-linearity of -0.7/+0.5 LSB and a random noise of 148.5 µVrms, both of which are sufficient for the sensor. Owing to the low power consumption ADC, the sensor showed a low power consumption of 2.32 W in conjunction with a high frame rate of 120 fps and a high resolution of 33 Mpixels. The quality of the images taken by the image sensor is good enough for use in full-spec Super Hi-Vision.