A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform
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概要
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Reed-Solomon (RS) codes are widely used in digital communication and storage systems. Unlike usual VLSI approaches, this paper presents a high throughput fully programmable Reed-Solomon decoder on a multi-core processor. The multi-core processor platform is a 2-Dimension mesh array of Single Instruction Multiple Data (SIMD) cores, and it is well suited for digital communication applications. By fully extracting the parallelizable operations of the RS decoding process, we propose multiple optimization techniques to improve system throughput, including: task level parallelism on different cores, data level parallelism on each SIMD core, minimizing memory access, and route length minimized task mapping techniques. For RS(255,239,8), experimental results show that our 12-core implementation achieve a throughput of 4.35Gbps, which is much better than several other published implementations. From the results, it is predictable that the throughput is linear with the number of cores by our approach.
著者
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Yu Zhiyi
State Key Lab. Of Asic And System Department Of Microelectronics Fudan University
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HUANG Bei
State Key Lab of ASIC & System, Fudan University
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ZENG Xiaoyang
State Key Lab of ASIC & System, Fudan University
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CHEN Yun
State Key Lab of ASIC & System, Fudan University
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YOU Kaidi
State Key Lab of ASIC & System, Fudan University
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