A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS
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概要
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This paper details the design of a 64×32bit 4-read 2-write register file in TSMC 65nm LP process. The register file avoids cell banking with pseudo-differential sensing scheme. Moreover, this approach enables a fully shareable and completely symmetry cell layout which shows competitive area results. Non-full-swing technique is proposed to avoid over design and improve energy efficiency. As for the timing control module, clocked pull-down circuit cuts off a possible short-current path at high clock frequency. A prototype is implemented in TSMC 65nm LP technology. The measured results demonstrate operation of 0.77GHz, consuming 7.08mW at 1.2V, and occupying 0.018mm2.
著者
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Han Jun
State Key Laboratory For Advanced Metals And Materials University Of Science & Technology Beijing
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Yu Zhiyi
State Key Lab. Of Asic And System Department Of Microelectronics Fudan University
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Zeng Xiaoyang
State Key Lab Of Asic And System Fudan University
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ZENG Xiaoyang
State Key Laboratory of ASIC and System, Fudan University
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Xiong Baoyu
State Key Laboratory of ASIC and System, Fudan University
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Zhang Yuejun
Institute of Circuits and Systems, Ningbo University
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Zhang Xingxing
State Key Laboratory of ASIC and System, Fudan University
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Li Yi
State Key Laboratory of ASIC and System, Fudan University
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Zhang Zhang
School of Electronic Science and Applied Physics, Hefei University of Technology
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Cheng Xu
State Key Laboratory of ASIC and System, Fudan University
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ZENG Xiaoyang
State Key Lab of ASIC & System, Fudan University
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