Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm
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概要
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This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335Mbps and 176Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.
- The Institute of Electronics, Information and Communication Engineersの論文
- 2012-08-01
著者
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Han Jun
State Key Laboratory For Advanced Metals And Materials University Of Science & Technology Beijing
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HE Zhongzhu
State-Key Laboratory of ASIC and System, Fudan University
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HAN Jun
State-Key Laboratory of ASIC and System, Fudan University
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ZENG Xiaoyang
State-Key Laboratory of ASIC and System, Fudan University
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ZENG Xiaoyang
State Key Lab of ASIC & System, Fudan University
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ZHANG Yuli
State-Key Laboratory of ASIC and System, Fudan University
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WENG Xinqian
State-Key Laboratory of ASIC and System, Fudan University
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