A-1-18 Overlapped-voltage clock driver and low peak voltage evaluation for 2PASCL
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概要
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The paper proposes the best conditions for the power supply clocks of two-phase clocked adiabatic static CMOS logic (2PASCL) circuit by evaluating several overlapped clock combinations and measure the power dissipations using SPICE simulation. Then, the reduced peak driving voltage of 1.2 V for 2PASCL and CMOS are compared.
- 2010-03-02
著者
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Anuar Nazrul
Graduate School of Engineering, Gifu University
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Takahashi Yasuhiro
Faculty of Engineering, Gifu University
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Sekine Toshikazu
Faculty of Engineering, Gifu University
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Anuar Nazrul
Graduate School Of Engineering Gifu University
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Sekine Toshikazu
Faculty Of Engineering Gifu University
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Takahashi Yasuhiro
Faculty Of Engineering Gifu University
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SEKINE Toshikazu
Faculty Engineering Gifu University Japan
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TAKAHASHI Yasuhiro
Faculty Engineering Gifu University Japan
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