LSI Implementation of a Secure Low-Power CSSAL Cellular Multiplier

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概要

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• In this paper, a secure and low-power charge-sharing symmetric adiabatic logic cellular multiplier over GF(2^4) implemented in LSI using 0.18um CMOS process is presented. The verification of the logic functionality and the operating speed of the implemented LSI in adiabatic switching technique will be discussed. The correlation of LSI output logic function and the supply current trace are measured in order to analyze the current-to-data dependency in respect to the given input transitions. Maximum power clock frequency for chip measurement is 5 MHz, whereas the post-layout simulation is up to 50 MHz and the pre-layout simulation reaches 125 MHz using the same individual logic.

• 2013-09-19

著者

• TAKAHASHI Yasuhiro

  Faculty Engineering Gifu University Japan

• SEKINE Toshikazi

  Faculty Engineering, Gifu University

• TAKAHASHI Yasuhiro

  Faculty Engineering, Gifu University, Japan

• MONTEIRO Cando

  Graduate School of Engineering, Gifu University, Japan

関連論文

• A-1-18 Overlapped-voltage clock driver and low peak voltage evaluation for 2PASCL
• A-7-6 Investigation Study of Inner-cell Bit-Parallel Multiplier over GF(2^m) Using Secure Adiabatic Logic Style
• Survey on Secure Adiabatic Logic for Countermeasure against Side-Channel Attacks
• C-12-41 LSI Implementation of over GF(24) using Ad a Bit-Parallel Cellular Multi Charge-Sharing Symmetric iabatic Logic.plier
• Survey on Secure Adiabatic Logic for Countermeasure against Side-Channel Attacks
• LSI Implementation of a Secure Low-Power CSSAL Cellular Multiplier
• A-1-2 Measurement of CSSAL Multiplier over GF(2^4) LSI Implemented in 0.18μm CMOS Technology

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