De-Embedding Technique for the Extraction of Parasitic and Stray Capacitances from 1-Port Measurements(Printed Circuit Board,<Special Section>2nd Pan-Pacific EMC Joint Meeting-PPEMC'06-)

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A de-embedding technique for the measurement of very small parasitic capacitances of package or small module interconnects is presented. At high frequencies small parasitic capacitances become important, and measurement probes can strongly affect measurement results. The present technique is based on additional measurements with only one tip of the probe touching one conductor, while the second tip is kept floating on the substrate. A necessary condition for its application is that the measured capacitance does not depend on the position of the floating probe tip. Measurements with inverted probe tip polarities are also used. In this way, the capacitances between probe tips and DUT can be estimated together with the parasitic capacitances of interest. Depending on the required accuracy, de-embedding of different orders have been introduced, which consider capacitance configurations of increasing complexity. The technique requires the solution of one or more systems of non-linear equations. In the present example the minimization of the norm of the residual of the system has been treated as a least squares problem, and has been solved numerically with MATLAB. The accuracy of the measurement can be also approximately estimated with the residual. As application example, a small module with power and ground planes has been considered. Two different probes have been used. Even though the stray capacitances of the probes are very different, the values of the extracted parasitic capacitances are in agreement with each other. The accuracy has been verified also with simulation results. To this purpose, a combination of known formulas from the literature, a 2D Finite Element Method (FEM) tool and a 3D Boundary Element Method (BEM) tool have been used. A high accuracy can be obtained, even when a strong capacitive coupling between probe ground and DUT is present. The technique can be applied also when only a subset of measurement results are available.
社団法人電子情報通信学会の論文
2007-06-01

De-Embedding Technique for the Extraction of Parasitic and Stray Capacitances from 1-Port Measurements(Printed Circuit Board,<Special Section>2nd Pan-Pacific EMC Joint Meeting-PPEMC'06-)

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