Reverse current reduction of Ge pin photodiodes on Si without post-growth annealing (フォトニックネットワーク)
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概要
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A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post-growth annealing, the reverse current density is reduced to 〜10mA/cm^2 at -1V, i.e. one order of magnitude lower than that of the reference photodiode without i-Si layer. The responsivity of the Ge photodiode reaches the nearly theoretical maximum. This "non-thermal" approach to reduce reverse current should accelerate electronics-photonics convergence using Ge on the Si CMOS platform.
- 2009-01-22
著者
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Ishikawa Yasuhiko
Department Of Materials Engineering Graduate School Of Engineering The University Of Tokyo
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PARK Sungbong
Department of Materials Engineering, Graduate School of Engineering The University of Tokyo
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TAKITA Shinya
Department of Materials Engineering, Graduate School of Engineering The University of Tokyo
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OSAKA Jiro
Department of Materials Engineering, Graduate School of Engineering The University of Tokyo
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WADA Kazumi
Department of Materials Engineering, Graduate School of Engineering The University of Tokyo
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Osaka Jiro
Department Of Materials Engineering Graduate School Of Engineering The University Of Tokyo
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Wada Kazumi
Department Of Materials Engineering Graduate School Of Engineering The University Of Tokyo
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Takita Shinya
Department Of Materials Engineering Graduate School Of Engineering The University Of Tokyo
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Takita Shinya
Department Of Applied Chemistry Faculty Of Engineering Kumamoto University
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Park Sungbong
Department Of Materials Engineering Graduate School Of Engineering The University Of Tokyo
関連論文
- Reverse current reduction of Ge pin photodiodes on Si without post-growth annealing (フォトニックネットワーク)
- Reverse current reduction of Ge pin photodiodes on Si without post-growth annealing
- Reverse current reduction of Ge pin photodiodes on Si without post-growth annealing (光エレクトロニクス)
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