9 ps Gate Delay Josephson OR Gate with Modified Variable Threshold Logic

概要

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A Josephson logic OR gate suitable for high speed logic circuits is proposed and tested. This gate has a structure modified from Variable Threshold Logic (VTL) to obtain large operating margin and small occupation area. The operating margin is calculated as ±19% for fan-out of 2, even with the critical current variation of ±20%. The circuit area is 40×60μm^2. A chain of 5-stage OR gates was fabricated. The gates had Josephson junctions of 4 μm and 7 μm diameter made with Pb-alloy technology. The minimum gate delay of 9 ps was measured using a Josephson sampler.
社団法人応用物理学会の論文
1985-01-20