The Design of a 2.7V, 200MS/s, and 14-Bit CMOS D/A Converter with 63dB of SFDR Characteristics for the 90MHz Output Signal(<Special Issue>Devices and Circuits for Next Generation Multi-Media Communication Systems)
スポンサーリンク
概要
- 論文の詳細を見る
This paper describes the design of a 2.7V operational, 200MS/s, 14-bit CMOS D/A converter (DAG). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63dB of SFDR characteristics for the 90MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7V, the clock rate is 200MS/s, and the power dissipation is estimated to be 300mW.
- 社団法人電子情報通信学会の論文
- 2003-06-01
著者
-
SUGIMOTO Yasuhiro
Department of Physics, Kyoto University
-
Sakurai Hiroki
Graduate School Of E. E. And C. Eng. Chuo University
-
Sugimoto Yasuhiro
Department Of Electrical Electronic And Communication Engineering Chuo University
-
SUGIMOTO Yasuhiro
Department of EECE, Chuo University
関連論文
- The Design and Performance of Multiwire Proportional Chambers for High Flux Beam Monitoring
- A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications(Analog Circuit and Device Technologies)
- A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture(Analog Signal Processing)
- The Design of a 2.7V, 200MS/s, and 14-Bit CMOS D/A Converter with 63dB of SFDR Characteristics for the 90 MHz Output Signal
- The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25V of Output Voltage Using a Fractional V_ Amplification Scheme(Electronic Circuits)
- A 2V, 500MHz and 3V, 920MHz Low-Power Current-Mode 0.6μm CMOS VCO Circuit (Special Issue on Microwave and Millimeter Wave Technology)
- Simulating Adaptive Human Bipedal Locomotion Based on Phase Resetting Using Foot-Contact Information
- Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit (Special Section of Letters Selected from the 1995 Society Conference of IEICE)
- Design of a Low-Voltage, Low-Power, High-Frequency CMOS Current-Mode VCO Circuit by Using 0.6μm MOS Devices (Special Section on Analog Circuit Techniques for System-on-Chip Integration)
- Demonstration and Analysis of Quadrupedal Passive Dynamic Walking
- Stabilizing Function of the Musculoskeletal System for Periodic Motion
- Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme(Analog Circuit Techniques and Related Topics)
- The Design of a 2.7V, 200MS/s, and 14-Bit CMOS D/A Converter with 63dB of SFDR Characteristics for the 90MHz Output Signal(Devices and Circuits for Next Generation Multi-Media Communication Systems)
- A 500-MHz and 60-dBΩ CMOS Transimpedance Amplifier Using the New Feedforward Stabilization Technique(Optical, Analog Circuit and Device Technologies)
- A Study of Effective Power-Reduction Methods for PDP Address-Driver ICs by Applying a Power-Dispersion Scheme(Electronic Displays)
- A Current-Mode Bit-Block Circuit Applicable to Low-Voltage, Low-Power Pipeline Video-Speed A/D Converters (Special Section on Analog Technologies in Submicron Era)
- A 1MHz, Synchronous, Step-down from 3.6V to 1V, PWM CMOS DC-DC Converter with more than 80% of Power Efficiency(Electronic Circuits)