Study of a Low Voltage, Low Power and High Frequency CMOS VCO Circuit (Special Section of Letters Selected from the 1995 Society Conference of IEICE)
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概要
- 論文の詳細を見る
This paper examines the feasibility of a high frequency (more than 1 GHz) ring-oscillator-type CMOS VCO, able to maintain a good linearity between the oscillator output frequency and control voltage, while preserving low voltage and low power operation capabilities. A CMOS VCO circuit, with a newly developed current-controlled delay cell and an architecture combining the transitions of each delay cell output, with high-frequency operation, was designed and simulated using the CMOS 0.6 μm device parameters. We analyzed the generation of unnecessary harmonics and sub-harmonics when a delay cell's propagation delay time varied. The simulation indicated that a CMOS VCO with a frequency range of 200 MHz to 1.4 GHz, a power dissipation of 8.5 mW at 900 MHz from a 3 V power supply, and an operation voltage of 1 V to 3 V can be implemented on a chip.
- 社団法人電子情報通信学会の論文
- 1996-05-25
著者
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SUGIMOTO Yasuhiro
Department of Physics, Kyoto University
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Sugimoto Y
Chuo Univ. Tokyo Jpn
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Tsuji T
Hiroshima Univ. Higashi‐hiroshima‐shi Jpn
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Tsuji Takaaki
Department Of Orthopaedic Surgery Douaikai Hospital
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Tsuji Takaaki
Department Of Electrical And Electronics Engineering Chuo University
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SUGIMOTO Yasuhiro
Department of EECE, Chuo University
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