The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25V of Output Voltage Using a Fractional V_<BE> Amplification Scheme(Electronic Circuits)

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概要

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• This paper describes a CMOS voltage reference circuit which occupies small die area and has less than 1.25V of output voltage. The reference voltage is determined by a resistor ratio, and it is possible to set the reference voltage from zero to near the supply voltage with the same temperature independence as those of Widlar's and Brokaw's bandgap voltage references. The temperature-independent reference voltage is formed by adding two voltages: the amplified fractional V_<BE> (base-to-emitter voltage) of a bipolar transistor with a negative TC (temperature coefficient) and the amplified V_T (thermal voltage) with a positive TC. When a reference voltage smaller than 1.25V is required, the voltage gain of the amplifier for V_<BE> becomes less than one, and the voltage gain of the amplifier for V_T becomes small. This enables the size of bipolar transistors for V_T generation to be small. The proposed voltage reference circuit was implemented in a standard 0.35-μm CMOS technology. A temperature-independent current source was also obtained from the same circuit. The results were a TC (temperature coefficient) of 46ppm/℃ over 130℃ change, a line regulation of 2.2mV/V for the 0.5V reference voltage with 8.7μA of current consumption in the voltage reference part, and a 6% change over 130℃ change for the 13μA current source.

• 社団法人電子情報通信学会の論文
• 2007-02-01

著者

• SAKURAI Hiroki

  Graduate School of E., E., and C. Eng., Chuo University

• SUGIMOTO Yasuhiro

  Dept. of E., E., and C. Eng., Chuo University

• Sakurai Hiroki

  Graduate School Of E. E. And C. Eng. Chuo University

• Sugimoto Yasuhiro

  Dept. Of E. E. And C. Eng. Chuo University

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• The Design of a 2.7V, 200MS/s, and 14-Bit CMOS D/A Converter with 63dB of SFDR Characteristics for the 90 MHz Output Signal
• The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25V of Output Voltage Using a Fractional V_ Amplification Scheme(Electronic Circuits)
• Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme(Analog Circuit Techniques and Related Topics)
• The Design of a 2.7V, 200MS/s, and 14-Bit CMOS D/A Converter with 63dB of SFDR Characteristics for the 90MHz Output Signal(Devices and Circuits for Next Generation Multi-Media Communication Systems)

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