A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture(Analog Signal Processing)

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This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained results are digital codes at the output of the ADC, and they contain positive and negative errors in turn. The two consecutive codes are then added in digital form, thus canceling the errors. This results in the two-fold oversampling operation. As the distortion component arises when the input signal frequency increases, a frontend SHA is used to completely eliminate distortion up to the Nyquist frequency. The behavioral simulation of a 14-bit ADC reveals that this CMOS pipelined ADC with a 1.5-bit bit-block architecture, even without a frontend SHA, has more than 70dB of spurious-free dynamic range (SFDR) for up to an 8MHz input signal when each of the upper three bit-blocks has gain and offset errors of +0.8% when the clock frequency is 102.4MHz. Using an SHA in front further improves the SFDR to 95dB up to the signal frequency bandwidth of 25.6MHz.
社団法人電子情報通信学会の論文
2007-10-01