Compaction of Test Sets for Combinatinal Circuits Based on Symbolic Fault Simulation (Special Issue on Synthesis and Verification of Hardware Design)

概要

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Since the time required for testing logic circuits is proportional to the number of test vectors, the size of test sets as well as test generation time is one of the most important factors to be considered in test generation. The size of test sets becomes an essential issue, especially for scan designed circuits, because of the need to shift a test vector serially into the scan path. In this paper, we propose new methods of generating compact test sets to detect all the irredundant single stuck-at faults in combinatinal circuits. The proposed algorithms calculate a test function for each fault which corresponds to the set of all test vectors for the fault and generate a compact test set by analyzing the test functions. The analysis is based on finding a test vector which detects the largest number of remaining faults. Since our methods select a test vector among all the test vectors, represented by a test function, for a target fault, smaller test sets can be generated, in general, than that by conventional test set compaction methods. The experimental results show that the size of test sets generated by our method is about one-third as large as that without compaction.
社団法人電子情報通信学会の論文
1993-09-25