Ishiura Nagisa | Faculty Of Engineering Osaka University

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概要

• 同名の論文著者
• Faculty Of Engineering Osaka Universityの論文著者

関連著者

• Ishiura Nagisa

  Faculty Of Engineering Osaka University

• SHIRAKAWA Isao

  Faculty of Engineering, Osaka University

• YAMADA Akihisa

  Faculty of Pharmaceutical Sciences, Kobe-Gakuin University

• Ishiura N

  Osaka Univ. Suita‐shi Jpn

• Ishiura Nagisa

  Faculty Of Information System Engineering Osaka University

• Shirakawa Isao

  Faculty Of Engineering Osaka University

• Yamada Akihisa

  The Design Technology Development Laboratory Integrated Circuits Development Group Sharp Corporation

• Yamada Akihisa

  Faculty Of Pharmaceutical Sciences Kobe-gakuin University

• YAMAUCHI Hitoshi

  Faculty of Science and Technology, Science University of Tokyo

• Yamauchi Hitoshi

  Faculty Of Science And Technology Science University Of Tokyo

• Takahashi Hiromitsu

  Faculty Of Computer Science And System Engineering Okayama Prefectural University

• Yajima Shuzo

  Faculty Of Engineering Kyoto University

• HIGUCHI Hiroyuki

  Faculty of Health and Science, Kyushu University of Health and Welfare

• Yamazaki Toshiki

  Faculty of Engineering, Osaka University

• Kambe Takashi

  Precision Technology Development Center, SHARP Corporation

• Kambe T

  Sharp Corp. Tenri‐shi Jpn

• Yamazaki Toshiki

  Faculty Of Engineering Osaka University

• Yamada Akihiko

  The Department Of Electrical Engineering Graduate School Of Engineering Tokyo Metroporitan Universit

• Yamada Akihiko

  Department Of Electrical Engineering Graduate School Of Engineering Tokyo Metropolitan University

• Higuchi Hiroyuki

  Faculty Of Engineering Kyoto University

• Yamauchi Hitoshi

  Faculty Of Computer Science And System Engineering Okayama Prefectural University

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著作論文

• Implicit Representation and Manipulation of Binary Decision Diagrams (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
• Datapath Scheduling for Behavioral Description with Conditional Branches (Special Section on VLSI Design and CAD Algorithms)
• Compaction of Test Sets for Combinatinal Circuits Based on Symbolic Fault Simulation (Special Issue on Synthesis and Verification of Hardware Design)
• Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams (Special Issue on Synthesis and Verification of Hardware Design)

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