Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams (Special Issue on Synthesis and Verification of Hardware Design)

スポンサーリンク

概要

• 論文の詳細を見る

• In this paper, a new method of synthesizing multi-level logic circuits directly from binary decision diagrams (BDDs) is proposed. In the simple multiplexer implementation, the depth of the synthesized circuit was always O(n), where n is the number of input variables. The new synthesis method attempts to reduce the depth of circuits. The depth of the synthesized circuits is O(log n log w) where w is the maximum width of given BDDs. The synthesized circuits are 2-rail-input -rail-output logic circuits. The circuits have good testability; it is proved that the circuits are robustly path-delay fault testable and also totally self-checking for single stuck-at faults.

• 社団法人電子情報通信学会の論文
• 1993-09-25

著者

• Ishiura Nagisa

  Faculty Of Engineering Osaka University

関連論文

• Implicit Representation and Manipulation of Binary Decision Diagrams (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
• Datapath Scheduling for Behavioral Description with Conditional Branches (Special Section on VLSI Design and CAD Algorithms)
• Compaction of Test Sets for Combinatinal Circuits Based on Symbolic Fault Simulation (Special Issue on Synthesis and Verification of Hardware Design)
• Synthesis of Multilevel Logic Circuits from Binary Decision Diagrams (Special Issue on Synthesis and Verification of Hardware Design)

スポンサーリンク