Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses (Special Section on Discrete Mathematics and Its Applications)
スポンサーリンク
概要
- 論文の詳細を見る
Ordered Binary Decision Diagrams (OBDDs) are graph-based representations of Boolean functions which are widely used because of their good properties. In this paper, we introduce nondeterministic OBDDs (NOBDDs) and their restricted forms, and evaluate their expressive power. In some applications of OBDDs, canonicity, which is one of the good properties of OBDDs, is not necessary. In such cases, we can reduce the required amount of storage by using OBDDs in some non-canonical form. A class of NOBDDs can be used as a non-canonical form of OBDDs. In this paper, we focus on two particular methods which can be regarded as using restricted forms of NOBDDs. Our aim is to show how the size of OBDDs can be reduced in such forms from theoretical point of view. Firstly, we consider a method to solve satisfiability problem of combinational circuits using the structure of circuits as a key to reduce the NOBDD size. We show that the NOBDD size is related to the cutwidth of circuits. Secondly, we analyze methods that use OBDDs to represent Boolean functions as sets of product terms. We show that the class of functions treated feasibly in this representation strictly contains that in OBDDs and contained by that in NOBDDs.
- 社団法人電子情報通信学会の論文
- 1997-04-25
著者
-
TAKAGI Kazuyoshi
Graduate School of Information Science, Nagoya University
-
Takagi Kazuyoshi
Graduate School Of Information Schience Nara Institute Of Schience And Technology
-
NITTA Koyo
Faculty of Information Science, Kyoto University
-
BOUNO Hironori
Faculty of Information Science, Kyoto University
-
TAKENAGA Yasuhiko
Faculty of Information Science, Kyoto University
-
YAJIMA Shuzo
Faculty of Information Science, Kyoto University
-
Nitta Koyo
Faculty Of Information Science Kyoto University:ntt Lsi Laboratories
-
Yajima Shuzo
Faculty Of Engineering Kyoto University
-
Yajima Shuzo
Faculty Of Information Science Kyoto University
-
Bouno Hironori
Faculty Of Information Science Kyoto University
-
Takenaga Yasuhiko
Faculty Of Information Science Kyoto University
-
Takenaga Yasuhiko
Faculty Of Engineering Kyoto University
関連論文
- A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
- A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
- Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses (Special Section on Discrete Mathematics and Its Applications)
- Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees (Special Section on Discrete Mathematics and Its Applications)
- Formal Design Verification of Combinational Circuits Specified by Recurrence Equations (Special Issue on Synthesis and Verification of Hardware Design)
- Computational Complexity of Manipulating Binary Decision Diagrams
- On Parallel Computation Time of Unification for Restricted Terms
- On the Computational Power of Binary Decision Diagrams
- Hardware Algorithms and Logic Design Automation : An Overview and Progress Report
- Area-Time Efficient Evaluation of Elementary Functions
- Exponential Lower Bounds on the Size of Variants of OBDD Representing Integer Division
- Compaction of Test Sets for Combinatinal Circuits Based on Symbolic Fault Simulation (Special Issue on Synthesis and Verification of Hardware Design)