A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
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概要
- 論文の詳細を見る
In this paper, a fast and memory-efficient VLSI architecture for output probability computations of continuous Hidden Markov Models (HMMs) is presented. These computations are the most time-consuming part of HMM-based recognition systems. High-speed VLSI architectures with small registers and low-power dissipation are required for the development of mobile embedded systems with capable human interfaces. We demonstrate store-based block parallel processing (StoreBPP) for output probability computations and present a VLSI architecture that supports it. When the number of HMM states is adequate for accurate recognition, compared with conventional stream-based block parallel processing (StreamBPP) architectures, the proposed architecture requires fewer registers and processing elements and less processing time. The processing elements used in the StreamBPP architecture are identical to those used in the StoreBPP architecture. From a VLSI architectural viewpoint, a comparison shows the efficiency of the proposed architecture through efficient use of registers for storing input feature vectors and intermediate results during computation.
- (社)電子情報通信学会の論文
- 2010-02-01
著者
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NAKAMURA Kazuhiro
Graduate School of Information Science, Nagoya University
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YAMAMOTO Masatoshi
Graduate School of Information Science, Nagoya University
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TAKAGI Kazuyoshi
Graduate School of Information Science, Nagoya University
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TAKAGI Naofumi
Graduate School of Information Science, Nagoya University
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Yamamoto Masatoshi
Graduate School Of Information Science Nagoya University
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Takagi Kazuyoshi
Nagoya Univ. Nagoya‐shi Jpn
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Takagi Kazuyoshi
Graduate School Of Information Science Nagoya University
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Takagi Kazuyoshi
Graduate School Of Information Schience Nara Institute Of Schience And Technology
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Takagi Naofumi
Graduate School Of Information Science Nagoya University
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Takagi Naofumi
Graduate School Of Informatics Kyoto University
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Nakamura Kazuhiro
Graduate School Of Information Science Nagoya University
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Takagi Naofumi
Department Of Communications And Computer Engineering Kyoto University
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