Comparisons of Synchronous-Clocking SFQ Adders
スポンサーリンク
概要
- 論文の詳細を見る
Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles. In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms, called hardware algorithms, from different point of view than CMOS circuits, because SFQ circuits work by pulse logic while CMOS circuits work by level logic. In this paper, we compare implementations of hardware algorithms for addition by synchronous-clocking SFQ circuits. We show that a set of individual bit-serial adders and Kogge-Stone adder are superior to others.
- 2010-04-01
著者
-
TANAKA Masamitsu
Department of Information Engineering, Nagoya University
-
Takagi Naofumi
Department Of Information Engineering Nagoya University
-
Tanaka Masamitsu
Department Of Information Engineering Nagoya University
-
Tanaka Masamitsu
Department Of Electronics Nagoya University
-
Takagi Naofumi
Department Of Communications And Computer Engineering Kyoto University
関連論文
- Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm
- A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits(Superconducting Electronics)
- Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams(VLSI Design Technology and CAD)
- Floating-Point Euclidean Norm Computing Circuit
- Digit-Recurrence Algorithm for Computing Reciprocal Square-Root(Regular Section)
- A Hardware Algorithm for Integer Division Using the SD2 Representation(VLSI Design Technology and CAD)
- A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
- Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees (Special Section on Discrete Mathematics and Its Applications)
- Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits
- Bit-Serial Single Flux Quantum Microprocessor CORE
- 100GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10kA/cm^2 Nb Multi-Layer Process
- Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A^* Algorithm
- A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits
- High-Speed Demonstration of SFQ Circuit Based on Cell-Based Design Method
- Suppression of gastric cancer dissemination by ephrin-B1-derived peptide
- Comparisons of Synchronous-Clocking SFQ Adders
- Pipelined Bipartite Modular Multiplication
- Pipelined Bipartite Modular Multiplication
- Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector(VLSI Design Technology and CAD)
- Pipelined Bipartite Modular Multiplication
- Pipelined Bipartite Modular Multiplication
- Fast Modular Multiplication by Processing the Multiplier from Both Sides in Parallel
- Fast Modular Multiplication by Processing the Multiplier from Both Sides in Parallel
- Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits
- Fast Modular Multiplication by Processing the Multiplier from Both Sides in Parallel
- A Digit-Recurrence Algorithm for Cube Rooting
- Sphenoid Sinusitis Associated with Meningitis, Visual Disturbances and Total Ophthalmoplegia
- A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm(VLSI Design Technology and CAD)
- A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition
- Lupus anticoagulant as a risk factor for cerebral infarction and habitual abortions.