Pipelined Bipartite Modular Multiplication
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概要
- 論文の詳細を見る
We propose a fast hardware algorithm for calculating modular multiplication. This algorithm is based on the recently proposed bipartite modular multiplication method. The calculation of the modular multiplication is performed in the KT-residue system which enables the splitting of the multiplier into two parts which can then be processed in parallel. In the hardware algorithm that we propose, the addition of the partial products to the intermediate accumulated product is pipelined in order to reduce the critical path delay. A radix-4 version of the hardware algorithm is given and its hardware implementation is discussed.
- 社団法人電子情報通信学会の論文
- 2005-11-24
著者
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Takagi Naofumi
Department Of Information Engineering Nagoya University
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KAIHARA Marcelo
Department of Information Engineering, Nagoya University
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Kaihara Marcelo
Department Of Information Engineering Nagoya University
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Takagi Naofumi
Department Of Communications And Computer Engineering Kyoto University
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