A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition

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概要

• 論文の詳細を見る
• 2012-04-01

著者

• TAKAGI Kazuyoshi

  the Graduate School of Information Science, Nara Institute of Science and Technology

• Yamamoto Masatoshi

  Graduate School Of Information Science Nagoya University

• Takagi Kazuyoshi

  Nagoya Univ. Nagoya‐shi Jpn

• Takagi Kazuyoshi

  Graduate School Of Information Science Nagoya University

• Nakamura Kazuhiro

  The Graduate School Of Information Science Nara Institute Of Science And Technology

• Takagi Naofumi

  Graduate School Of Information Science Nagoya University

• Takagi Naofumi

  Department Of Communications And Computer Engineering Kyoto University

• Shimazaki Ryo

  The Graduate School Of Information Science Nagoya University

• Takagi Naofumi

  The Graduate School Of Informatics Kyoto University

• Yamamoto Masatoshi

  The Graduate School Of Information Science Nagoya University

• Nakamura Kazuhiro

  The Graduate School Of Information Science Nagoya University

• TAKAGI Kazuyoshi

  the Graduate School of Informatics, Kyoto University

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