A C-Testable Multiple-Block Carry Select Adder

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概要

• 論文の詳細を見る

• We propose a C-testable multiple-block carry select adder with respect to the cell fault model. Full adders and 2: 1 multiplexers are considered as cells. By an additional external input, we obtain a C-testable carry select adder. We only modify the least significant position of each block. The adder is testable with a test set consisting of 16 patterns regardless of the size of each block and the number of blocks. This is the minimum test set for the adder. We show two gate-level implementations of the adder which are testable with a test set of 9 patterns and 7 patterns respectively, with respect to the single stuck-at fault model.

• 2012-04-01

著者

• Kito Nobutaka

  Graduate School Of Informatics Kyoto University

• Takagi Naofumi

  The Graduate School Of Informatics Kyoto University

• Kito Nobutaka

  The Graduate School Of Informatics Kyoto University

• FUJII Shinichi

  the Graduate School of Information Science, Nagoya University

関連論文

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• A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition
• A C-Testable Multiple-Block Carry Select Adder

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