A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier

スポンサーリンク

概要

• 論文の詳細を見る

• A C-testable 4-2 adder tree for an easily testable high-speed multiplier is proposed, and a recursive method for test generation is shown. By using the specific patterns that we call ‘alternately inverted patterns, ’ the adder tree, as well as partial product generators, can be tested with 14 patterns regardless of its operand size under the cell fault model. The test patterns are easily fed through the partial product generators. The hardware overhead of the 4-2 adder tree with partial product generators for a 64-bit multiplier is about 15%. By using a previously proposed easily testable adder as the final adder, we can obtain an easily testable high-speed multiplier.

• （社）電子情報通信学会の論文
• 2010-10-01

著者

• Takagi Naofumi

  Graduate School Of Informatics Kyoto University

• KITO Nobutaka

  Graduate School of Informatics, Kyoto University

• HANAI Kensuke

  Sanyo Semiconductor Co., Ltd.

• Kito Nobutaka

  Graduate School Of Informatics Kyoto University

• Hanai Kensuke

  Sanyo Semiconductor Co. Ltd.

関連論文

• A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing
• A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier
• A C-Testable Multiple-Block Carry Select Adder

スポンサーリンク