Hardware Algorithms and Logic Design Automation : An Overview and Progress Report
スポンサーリンク
概要
著者
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Yasuura Hiroto
Faculty Of Engineering Kyoto University
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YAJIMA Shuzo
Faculty of Information Science, Kyoto University
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Yajima Shuzo
Faculty Of Engineering Kyoto University
関連論文
- Computational Power of Nondeterministic Ordered Binary Decision Diagrams and Their Subclasses (Special Section on Discrete Mathematics and Its Applications)
- A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs)
- Formal Design Verification of Combinational Circuits Specified by Recurrence Equations (Special Issue on Synthesis and Verification of Hardware Design)
- A Multi-Application Smart Card System with Authentic Post-Issuance Program Modification
- Computational Complexity of Manipulating Binary Decision Diagrams
- On Parallel Computation Time of Unification for Restricted Terms
- On the Computational Power of Binary Decision Diagrams
- Hardware Algorithms and Logic Design Automation : An Overview and Progress Report
- Area-Time Efficient Evaluation of Elementary Functions
- Exponential Lower Bounds on the Size of Variants of OBDD Representing Integer Division
- Compaction of Test Sets for Combinatinal Circuits Based on Symbolic Fault Simulation (Special Issue on Synthesis and Verification of Hardware Design)